As progress in Digital-to-Analog Converter (DACs) technology continues to yield devices capable of operating at greater and greater conversion rates, they are capable of supporting an increasing number of applications. For example, very high-speed DACs enable digital processing in applications that had once been limited to the analog domain. Such applications include wired and wireless communication systems. See for example, A. Rofougaran et al., “A single-chip 900-MHz Spread-Spectrum Wireless Transceiver in 1-μm CMOS—Part I: Architecture and Transmitter Design,” IEEE Int. J. of Solid-State Circuits, vol. 33, no. 4, April 1998, incorporated herein by reference in its entirety. These new applications often demand greater control of harmonic distortion and limitations in power consumption.
One emerging DAC architecture is a pipeline, switched-capacitor DAC as described in “A Quasi-Passive CMOS Pipeline D/A Converter,” by F. J. Wang, G. C. Temes, S. Law, published in the IEEE Int. J. of Solid-State Circuits, vol. 24, no. 6, December 1989, (the “Wang” reference) incorporated herein by reference in its entirety. An attractive characteristic of this architecture is that it intrinsically does not suffer from major output glitches, which are a common source of distortion in DACs. On the other hand, current implementations are affected by a number of other circuit shortcomings that limit the practically achievable dynamic linearity.
A conventional switched-capacitor, pipeline DAC is composed by cascading a number of substantially identical cells that cooperatively synthesize an analog representation of a digital quantity by a charge-sharing algorithm driven by input digital data. Each cell includes a storage capacitor and is uniquely associated to a respective bit of the digital input. The capacitor is used to store an intermediate result of the data conversion and further as a processing element for the conversion algorithm. In more detail, each capacitor in the pipeline of cells is pre-charged to one of two different reference voltage levels depending on the logic state of the bit associated with the cell. This type of switched-capacitor DAC is discussed in more detail below.
At least one problem with this approach relates to the settling behavior of the capacitors' pre-charge process. Namely, the settling behavior depends on the digital code to be converted. Thus, the settling behavior for a cell associated with a logical “1” input will be different than the settling behavior of the same cell associated with a logical “0.” This result is referred to as a “code dependence” that leads to a degradation in the linearity of the DAC. Further complicating matters, the source circuit providing the reference voltage levels is also disturbed by the pre-charge process. This disturbance is also code-dependent and further limits linearity.